A sample and hold (S/H) circuit is an analog device that samples, e.g., captures, the voltage of an input analog signal and holds its value, e.g., keeping it at a constant level for a period of time regardless of the changes of the input signal. Sample and hold circuits can be considered as the elementary analog memory devices. Sample and hold circuits can be used in analog-to-digital converters to eliminate variations in input signal that can corrupt the conversion process.
A typical sample and hold circuit can use a capacitor to maintain the constant output level when the input signal changes. To sample the input voltage, a switch, such as a field effect transistor (FET) switch, can connect the input voltage to the capacitor so that the voltage across the capacitor is practically equal, or proportional to, the input voltage. An operation amplifier can be used to improve the input impedance and the charge or discharge rate of the capacitor. In hold mode, the switch disconnects the capacitor from the input voltage. The capacitor provides a constant output voltage that is equal or proportional to the sampled input voltage. The capacitor will eventually discharge, for example, by its leakage current and the load currents, so the hold time of the sample and hold circuit is determined by the voltage drop within an acceptable error margin.
FIGS. 1A-1C illustrate a schematic behavior of a prior art sample and hold circuit. FIG. 1A shows a simple sample and hold circuit 100, including a capacitor 122 for holding the voltage and a FET switch 124 for sampling the input voltage. During the sample time, the FET switch is on so that the input Vin is connected to the capacitor 122, charging or discharging the capacitor 122 so that the voltage Vout across the capacitor 122 is equal to the input voltage Vin. During the hold time, the FET switch is off, and the input voltage Vin is disconnected from the capacitor 122 and the output voltage Vout. The output voltage Vout remains the same, e.g., held by the charges in the capacitor 122. Other components can be added to the sample and hold circuit 100, such as an operation amplifier before the FET switch 124 and another operation amplifier after the capacitor 122.
FIG. 1B shows a response function of the sample and hold circuit 100, which includes the values of the output voltages given the input voltages. During the sample times 152, the output voltages follow the variation of the input voltages. During the hold times 154, the output voltages remain constant, regardless of the changes in input voltages.
FIG. 1C shows the time evolutions of the input voltage 160 and output voltage 165. The input voltage 160 can vary with respect to time. At sampling times, the output voltage 165 captures the input voltage 160, and holds its value until the next sampling time. As shown, the output voltages at the sampling time are equal to the input voltages. There can be other responses, for example, the output voltage can be a function of the input voltage.
The sample and hold circuits discussed can have issues that need to be improved, such as capacitance charge injection during the switch transistor operation, the necessity of a settling time before the sampling time (e.g., for charging of the capacitance), and short holding time (due to capacitance discharge). Longer hold time can be obtained by using larger capacitance, but at the expense of longer settling time.
Therefore, there is a need for a sample and hold circuit that can meet the design criteria for advanced devices.